Generally, a circuit system integrated on a semiconductor chip is operated by receiving a supply voltage (Vcc) supplied from an outside source. A CMOS semiconductor chip usually uses a nominal single voltage of 5 V as the supply voltage. However, although a CMOS semiconductor chip is given a supply voltage tolerance of .+-.10%, the chip actually has an operating voltage in the range of 4 V to 6 V.
Usually, the circuit system of a CMOS semiconductor chip includes a signal delay circuit to achieve the purpose of a special circuit. In the CMOS circuit system, a signal delay circuit having a prescribed delay time is formed that uses the signal transmission delay time of the gate. For instance, a CMOS signal delay circuit using CMOS inverters is illustrated in FIG. 1A. This circuit comprises a first CMOS inverter DRV to drive a capacitive load CL according to an input signal VIN, and a second CMOS inverter BTT as a buffer amplifier for buffering and outputting a terminal voltage signal Vo of the capacitive load CL.
The terminal voltage signal Vo of the capacitive load CL has a delay characteristic with respect to the input signal VIN as shown in FIG. 1B. In detail, the capacitive load CL is charged by supply voltage Vcc through pull-up PMOS transistor PM and discharged by a ground voltage Vss or OV through pull-down NMOS transistor NM of the first CMOS inverter DRV. Therefore, the delay time Td is determined by the voltage fall time Tf and the voltage rise time Tr according to the following equation: ##EQU1##
Here, on the assumption that the threshold voltages VTN and VTP of the MOS transistors NM and PM are approximately 0.2 Vcc and the current driving capability .beta.N, .beta.P of the MOS transistors NM and PM are equal to each other, the above equation (1) can be rewritten as the following equation; ##EQU2##
Referring to the above equation (2), it is seen that the delay time Td is proportional to the capacitance of the capacitive load CL and inversely proportional to the supply voltage Vcc.
Accordingly, if the capacitance of the capacitive load CL is set to a fixed value, the delay time Td, as shown in FIG. 1C, varies inversely with respect to the fluctuation of the supply voltage Vcc.
Therefore, the effective load capacitance Ceff has a disadvantage in that the delay characteristic varies greatly according to the operating voltage level as a very small fluctuation of the effective load capacitance occurs according to the variation of the supply voltage Vcc.
Also, the variation of the delay characteristic according to the fluctuation of the operating voltage causes a race-around condition problem in high speed operation especially at a high operating voltage and is a cause of misoperation. In order to prevent this, if the delay time at the high operating voltage is lengthened, it greatly impedes the high speed operation at a low operating voltage. That's why the threshold voltages VTN, VTP of the transistors of the driving circuit DRV are set equal to the threshold voltages VTNL, VTPL of the capacitive load CL. Usually, the threshold voltage of an NMOS and PMOS capacitor can be easily controlled by implantation of III-V group elements, for example, Boron(B) phosphorous(P), or Arsenic(As), in the channel region of the capacitor before the deposition of polysilicon used as a gate electrode.